Phase-locked loops (PLLs) are common building blocks in wireless transceivers. They provide a reference signal used to modulate/demodulate data from baseband to radio frequency. In a digital PLL (DPLL), the phase of a voltage-controlled oscillator (VCO) is measured by a time-to-digital converter (TDC) and compared with a high-purity, low-frequency reference inside a phase detector. The phase detector produces a digital word being equal to the error phase, which is digitally filtered and then sent to digital-to-analog converter (DAC) in order to set the control voltage of the VCO. The VCO phase is measured and filtered in the digital domain rather than in analog PLL, thus both an analog-to-digital converter (ADC) and a DAC are used. The TDC acts as an ADC inside the DPLL by measuring the VCO phase and quantizing it to produce a digital word.
Typical implementations of the TDC use a delay line or a delay-locked loop (DLL). A DLL produces an integer number of equally spaced phases by dividing the input signal period into an integer number (equal to the number of delay elements used). The phase of the input signal is measured by sampling each phase of the DLL with a reference clock, with the sampled sequence (zeros and ones) containing the information on the phase to be measured. The resolution (e.g., the least significant bit (LSB)) of the TDC is equal to the delay introduced by each delay element in the DLL. The finite TDC resolution introduces quantization error which, under certain conditions, can be considered as a white noise. The coarser the time resolution, the higher the quantization noise. Since the TDC noise is added in the PLL feedback loop, the noise is low pass filtered by the PLL and it appears as PLL in band noise.
Wireless standards may call for integrated phase noise, e.g., noise inside the transmission channel, as low as −39 decibels relative to a carrier (dBc) for the local oscillator generation. Assuming a loop bandwidth of 1 Megahertz (MHz) and equal contribution to the total phase noise from the VCO and the TDC, the target TDC quantization noise may be −102 dBc/Hz. This target translates into a TDC time resolution, for a 2.7 gigahertz (GHz) carrier, of 10.2 picoseconds (ps). A conventional DLL-based TDC cannot achieve such a resolution since it is limited by the minimum delay of each controllable delay element (at least 20 ps).